# About the VVC category

**URL:** <https://forum.uvvm.org/t/about-the-vvc-category/177>\
**Category:** VVC\
**Created:** [May 11, 2021, 6:27pm UTC](https://forum.uvvm.org/t/about-the-vvc-category/177 "2021-05-11T18:27:00Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Marius](https://dub1.discourse-cdn.com/flex017/user_avatar/forum.uvvm.org/marius/32/43_2.png) [@Marius](https://forum.uvvm.org/u/Marius)\
**Post date:** [May 11, 2021, 6:27pm UTC](https://forum.uvvm.org/t/about-the-vvc-category/177/1 "2021-05-11T18:27:00Z")

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(Replace this first paragraph with a brief description of your new category. This guidance will appear in the category selection area, so try to keep it below 200 characters.)

Use the following paragraphs for a longer description, or to establish category guidelines or rules:

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**Author:** ![HighLevelDesign](https://avatars.discourse-cdn.com/v4/letter/h/ecd19e/32.png) [@HighLevelDesign](https://forum.uvvm.org/u/HighLevelDesign)\
**Post date:** [October 26, 2022, 3:21pm UTC](https://forum.uvvm.org/t/about-the-vvc-category/177/2 "2022-10-26T15:21:40Z")

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Hi Marius,

A few weeks back, I dug into the UVVM and specifically the Ethernet HVCC work. I create a testbench to help my understanding of the UVVM framewok and build a testbench to encapsulate one of our hardware Ethernet interface chips. I integrated the RGMII VVC into the HVCC framework so it support SBI/GMII/RGMII. I used the GMII as a reference for the modifications. If you interested in the work, let me know and I will push it to you. I am mostly involved on the waveform and modeling side, but my early roots are in HDL. 1029.1-1998 - IEEE Standard For VHDL Waveform and Vector Exchange (Waves) to Support Design and Test Verification … I used to use this process for most of my testbench work. Take care. Lloyd
