# Latest **URL:** https://forum.uvvm.org/latest.md [Latest](https://forum.uvvm.org/latest.md) · [Categories](https://forum.uvvm.org/categories.md) · [Tags](https://forum.uvvm.org/tags.md) --- ## [Welcome to Discourse](https://forum.uvvm.org/t/welcome-to-discourse/7)
**Author:** [@system](https://forum.uvvm.org/u/system)\ **Replies:** 0\ **Last updated:** [January 7, 2020, 12:24pm UTC](https://forum.uvvm.org/t/welcome-to-discourse/7 "2020-01-07T12:24:43Z")
This is a forum for UVVM users to discuss questions, challenges and best practices for UVVM based FPGA and ASIC VHDL verification. --- ## [Unable to use axi\_write in my project](https://forum.uvvm.org/t/unable-to-use-axi-write-in-my-project/433)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 3\ **Last updated:** [September 17, 2026, 10:24pm UTC](https://forum.uvvm.org/t/unable-to-use-axi-write-in-my-project/433 "2026-09-17T22:24:23Z")
Hi everyone! I’m new of UVVM and this is my first experience of verification design; anyway… I must test (with UVVM framework) one IP. This IP has a simle AXI memory mapped interface (ADDR, DATA, READY, VALID, LEN and S… --- ## [Simple testbench fails at time zero in Riviera with "Delta Overflow" error message](https://forum.uvvm.org/t/simple-testbench-fails-at-time-zero-in-riviera-with-delta-overflow-error-message/518)
**Author:** [@CharlesGardiner](https://forum.uvvm.org/u/CharlesGardiner)\ **Replies:** 0\ **Last updated:** [September 17, 2026, 10:06pm UTC](https://forum.uvvm.org/t/simple-testbench-fails-at-time-zero-in-riviera-with-delta-overflow-error-message/518 "2026-09-17T22:06:47Z")
A very simple testbench using four bitvis\_vip\_axi.axi\_vvc instances aborts a t time zero due to too many delta cycles, probably an infinite loop somewhere without a wait statement. KERNEL: Stopped at time 0 ps + 5000. … --- ## [AHB Slave VVC Implementation](https://forum.uvvm.org/t/ahb-slave-vvc-implementation/517)
**Author:** [@Veronica](https://forum.uvvm.org/u/Veronica)\ **Replies:** 1\ **Last updated:** [September 14, 2026, 11:00am UTC](https://forum.uvvm.org/t/ahb-slave-vvc-implementation/517 "2026-09-14T11:00:07Z")
Hello, I’m in the process of implementing an AHB VVC with both master and slave support. When implementing the slave receive BFM procedure I mostly took inspiration from axistream\_receive(). But this implementation star… --- ## [Forward looking check\_stable?](https://forum.uvvm.org/t/forward-looking-check-stable/515)
**Author:** [@Quant](https://forum.uvvm.org/u/Quant)\ **Replies:** 3\ **Last updated:** [June 22, 2026, 5:48pm UTC](https://forum.uvvm.org/t/forward-looking-check-stable/515 "2026-06-22T17:48:56Z")
I’d like to verify that a transfer does not start under certain conditions. For that I need to check that an appropriate signal stays ‘0’ for some time. I tried to the following: first check\_value to make sure it is ‘0… --- ## [Error in simulation, but waveform is correct](https://forum.uvvm.org/t/error-in-simulation-but-waveform-is-correct/516)
**Author:** [@Quant](https://forum.uvvm.org/u/Quant)\ **Replies:** 2\ **Last updated:** [June 22, 2026, 5:42pm UTC](https://forum.uvvm.org/t/error-in-simulation-but-waveform-is-correct/516 "2026-06-22T17:42:45Z")
Hi, I have a following problem. I verify correctness of a low active reset pulse (with Questa): await\_value(lmk\_resetn, '0', 0 ns, 100 ns, "Wait for reset to activate"); await\_stable(lmk\_resetn, 30 ns, FROM\_NOW, 60 n… --- ## [UVVM support GHDL open source simulator](https://forum.uvvm.org/t/uvvm-support-ghdl-open-source-simulator/46)
**Author:** [@omberge](https://forum.uvvm.org/u/omberge)\ **Replies:** 11\ **Last updated:** [June 22, 2026, 10:15am UTC](https://forum.uvvm.org/t/uvvm-support-ghdl-open-source-simulator/46 "2026-06-22T10:15:15Z")
Hello, I see that GHDL is a supported simulator for UVVM, but does anyone have a step-by-step tutorial how to compile and simulate using GHDL? --- ## [Check\_value vs assert\_value](https://forum.uvvm.org/t/check-value-vs-assert-value/512)
**Author:** [@Quant](https://forum.uvvm.org/u/Quant)\ **Replies:** 2\ **Last updated:** [March 16, 2026, 12:50pm UTC](https://forum.uvvm.org/t/check-value-vs-assert-value/512 "2026-03-16T12:50:29Z")
Hi, I am a new user to both UVVM and verification methodologies in general. I am currently studying documentation (which is a major reason for me to choose UVVM over OSVVM). I have a question: What is the difference be… --- ## [Cadence Xcelium support](https://forum.uvvm.org/t/cadence-xcelium-support/511)
**Author:** [@dankhav](https://forum.uvvm.org/u/dankhav)\ **Replies:** 1\ **Last updated:** [March 7, 2026, 6:16pm UTC](https://forum.uvvm.org/t/cadence-xcelium-support/511 "2026-03-07T18:16:19Z")
Hi, We are evaluating different simulator tools at my company and have so far managed to run UVVM in multiple simulators. But attempting to compile UVVM with Cadence Xcelium has been an exercise in frustration. It appea… --- ## [SPI VVC shift direction](https://forum.uvvm.org/t/spi-vvc-shift-direction/513)
**Author:** [@sigmuha](https://forum.uvvm.org/u/sigmuha)\ **Replies:** 0\ **Last updated:** [March 6, 2026, 8:47pm UTC](https://forum.uvvm.org/t/spi-vvc-shift-direction/513 "2026-03-06T20:47:08Z")
Hi! Would it be possible to add an option in the SPI VVC of which way to shift in and shift out data? Most usecases use MSB first, but some niche cases do require LSB first. I don’t have a good overview, but I might giv… --- ## [Running the Shipped UVVM TB Examples](https://forum.uvvm.org/t/running-the-shipped-uvvm-tb-examples/464)
**Author:** [@graemej](https://forum.uvvm.org/u/graemej)\ **Replies:** 5\ **Last updated:** [February 13, 2026, 12:23pm UTC](https://forum.uvvm.org/t/running-the-shipped-uvvm-tb-examples/464 "2026-02-13T12:23:38Z")
Trying to run the UART TB example from the most current release. Have followed the Getting Started instructions where I have my own folder sitting parallel to the UVVM download and I have compiled the uvvm\_util library … --- ## [New UVVM functionality: UVVM Assertions](https://forum.uvvm.org/t/new-uvvm-functionality-uvvm-assertions/509)
**Author:** [@EspenTa](https://forum.uvvm.org/u/EspenTa)\ **Replies:** 0\ **Last updated:** [January 18, 2026, 4:37pm UTC](https://forum.uvvm.org/t/new-uvvm-functionality-uvvm-assertions/509 "2026-01-18T16:37:49Z")
This is a new improvement emerging from the current ESA UVVM project. This brand new functionality will allow the use of simple but important assertions in your testbench - or even inside your DUT. The UVVM assertions a… --- ## [An UVVM case study](https://forum.uvvm.org/t/an-uvvm-case-study/507)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 0\ **Last updated:** [December 18, 2025, 8:37pm UTC](https://forum.uvvm.org/t/an-uvvm-case-study/507 "2025-12-18T20:37:28Z")
Hi everyone! In these days I pick-up an old (and finished) university project - the implementation of a CORDIC in vectoring mode and I told me: “Why don’t exercise my experience in UVVM usage to test it?” please note… --- ## [Is it possible to have an AXI LITE VVC as slave?](https://forum.uvvm.org/t/is-it-possible-to-have-an-axi-lite-vvc-as-slave/55)
**Author:** [@estudioFPGA](https://forum.uvvm.org/u/estudioFPGA)\ **Replies:** 3\ **Last updated:** [December 17, 2025, 1:06pm UTC](https://forum.uvvm.org/t/is-it-possible-to-have-an-axi-lite-vvc-as-slave/55 "2025-12-17T13:06:12Z")
Hello everyone, I have an entity whose interfaces are UART and AXI LITE Master. I managed to simulate the UART interfaces TX and RX with UVVM, but I am not able to set an AXI LITE VVC as slave connected to my Master int… --- ## [How to file a PR for a bug fix?](https://forum.uvvm.org/t/how-to-file-a-pr-for-a-bug-fix/505)
**Author:** [@MartinBoberTecmata](https://forum.uvvm.org/u/MartinBoberTecmata)\ **Replies:** 2\ **Last updated:** [November 20, 2025, 8:25am UTC](https://forum.uvvm.org/t/how-to-file-a-pr-for-a-bug-fix/505 "2025-11-20T08:25:13Z")
We have integrated UVVM tag 2024.10.08 into one of our projects and we recently found a bug that is still present on the current master branch. The fix is relatively simple (a one-liner) so I want to file a PR. Of cours… --- ## [Can I randomize the AXI4 VVC ready signal](https://forum.uvvm.org/t/can-i-randomize-the-axi4-vvc-ready-signal/506)
**Author:** [@beandigital](https://forum.uvvm.org/u/beandigital)\ **Replies:** 1\ **Last updated:** [November 20, 2025, 6:52am UTC](https://forum.uvvm.org/t/can-i-randomize-the-axi4-vvc-ready-signal/506 "2025-11-20T06:52:34Z")
Is it possible to randomize the full AXI4 bus ready signals? --- ## [Increase to Queue Size not acted on](https://forum.uvvm.org/t/increase-to-queue-size-not-acted-on/488)
**Author:** [@Pete](https://forum.uvvm.org/u/Pete)\ **Replies:** 4\ **Last updated:** [September 9, 2025, 2:34pm UTC](https://forum.uvvm.org/t/increase-to-queue-size-not-acted-on/488 "2025-09-09T14:34:41Z")
Hi, I’m getting the following error: UVVM: UVVM: \*\*\* TB\_WARNING #1 \*\*\* UVVM: 12875098160 ns UART\_VVC,1,RX UVVM: Queue is now at 950 of 1000 elements. UVVM: UVVM: UVVM: ==================… --- ## [V\_cmd.data Length Limitation in SPI VVC Prevents Sending More Than 31 Bytes](https://forum.uvvm.org/t/v-cmd-data-length-limitation-in-spi-vvc-prevents-sending-more-than-31-bytes/502)
**Author:** [@stsecen](https://forum.uvvm.org/u/stsecen)\ **Replies:** 1\ **Last updated:** [August 27, 2025, 7:52am UTC](https://forum.uvvm.org/t/v-cmd-data-length-limitation-in-spi-vvc-prevents-sending-more-than-31-bytes/502 "2025-08-27T07:52:22Z")
Hi, I’m currently using the UVVM SPI VVC in my verification environment. In my testbench, I configured the VVC with the following generics: GC\_DATA\_ARRAY\_WIDTH =\> 1523 However, when I try to send 229 bytes of data us… --- ## [Transaction info with questasim 2022.4](https://forum.uvvm.org/t/transaction-info-with-questasim-2022-4/500)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 3\ **Last updated:** [June 11, 2025, 7:01pm UTC](https://forum.uvvm.org/t/transaction-info-with-questasim-2022-4/500 "2025-06-11T19:01:52Z")
Hi I try to develop a DUT model and some custom VVCs, I start to develop all things with modelsim 10.6d, next I move to questasim 2022.4. When I run test under modelsim, model works well but all go wrong in questasim. I… --- ## [Exit the await\_completion method](https://forum.uvvm.org/t/exit-the-await-completion-method/496)
**Author:** [@EZA](https://forum.uvvm.org/u/EZA)\ **Replies:** 1\ **Last updated:** [May 6, 2025, 11:59am UTC](https://forum.uvvm.org/t/exit-the-await-completion-method/496 "2025-05-06T11:59:09Z")
Hi all, I want to know if there is a way to exit the await\_completion method. This is the scenario: I have a DUT with a GPIO and a VVC that checks this GPIO. In my TB I have a process for generate stimulus for the DUT… --- ## [Porting UVVM repo fixes to UVVM supplementary](https://forum.uvvm.org/t/porting-uvvm-repo-fixes-to-uvvm-supplementary/494)
**Author:** [@FEngineer](https://forum.uvvm.org/u/FEngineer)\ **Replies:** 1\ **Last updated:** [April 23, 2025, 7:19am UTC](https://forum.uvvm.org/t/porting-uvvm-repo-fixes-to-uvvm-supplementary/494 "2025-04-23T07:19:51Z")
Will UVVM repo updates and fixes be ported to the UVVM\_Supplementary repo? --- ## [Problem with GC\_INSTANCE\_IDX in vip\_gpio](https://forum.uvvm.org/t/problem-with-gc-instance-idx-in-vip-gpio/492)
**Author:** [@Jorge](https://forum.uvvm.org/u/Jorge)\ **Replies:** 2\ **Last updated:** [April 21, 2025, 3:15pm UTC](https://forum.uvvm.org/t/problem-with-gc-instance-idx-in-vip-gpio/492 "2025-04-21T15:15:28Z")
Hi, I am facing an issue that I do not see how to solve. As starter, I just cloned today the latest version, just in case this issue was already fixed/addressed. I have testbench (TB) with two different test harnesses(T… --- ## [How often questions are answered in this forum?](https://forum.uvvm.org/t/how-often-questions-are-answered-in-this-forum/490)
**Author:** [@AlexK](https://forum.uvvm.org/u/AlexK)\ **Replies:** 1\ **Last updated:** [April 15, 2025, 5:30pm UTC](https://forum.uvvm.org/t/how-often-questions-are-answered-in-this-forum/490 "2025-04-15T17:30:15Z")
Unfortunately I see this forum is not as active as OSVVM. Responses take a lot of time or never get answered. One reason to go with OSVVM. --- ## [VVC Pipelined and out of order transactions](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489)
**Author:** [@AlexK](https://forum.uvvm.org/u/AlexK)\ **Replies:** 1\ **Last updated:** [April 15, 2025, 5:17pm UTC](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489 "2025-04-15T17:17:00Z")
Hallo, how do I tell to my testbench to pipeline the transcations with a single command ? Currently I use the await\_completion(…) command after every axi\_write or axi\_read. Is there a way to tell the VVC to always carry… --- ## [Problem with AXILITE VVC and Interrupts](https://forum.uvvm.org/t/problem-with-axilite-vvc-and-interrupts/486)
**Author:** [@AlexK](https://forum.uvvm.org/u/AlexK)\ **Replies:** 3\ **Last updated:** [April 11, 2025, 1:42pm UTC](https://forum.uvvm.org/t/problem-with-axilite-vvc-and-interrupts/486 "2025-04-11T13:42:34Z")
I use the Axi4Lite VVC as a master to access an AXI slave in the DUT from two different processes. One of the processes is checking on and interrupt coming from the DUT/slave indicating an arriving data. How do I make su… --- ## [GPIO\_CHECK\_STABLE is not ignoring changes on bits I define as don't care. Bug?](https://forum.uvvm.org/t/gpio-check-stable-is-not-ignoring-changes-on-bits-i-define-as-dont-care-bug/475)
**Author:** [@gfragoza1](https://forum.uvvm.org/u/gfragoza1)\ **Replies:** 5\ **Last updated:** [March 17, 2025, 6:35pm UTC](https://forum.uvvm.org/t/gpio-check-stable-is-not-ignoring-changes-on-bits-i-define-as-dont-care-bug/475 "2025-03-17T18:35:35Z")
I have 5 signals of an SLV hooked up to a GPIO VVC. They are outputs of the DUT. I just want to make sure that the MSB has remained stable ‘0’ for the previous 5 ms. Here is a snippet of my code: wait for 5 ms; gpio\_ch… --- ## [SoCMake now supports UVVM](https://forum.uvvm.org/t/socmake-now-supports-uvvm/474)
**Author:** [@Risto97](https://forum.uvvm.org/u/Risto97)\ **Replies:** 4\ **Last updated:** [February 2, 2025, 11:33am UTC](https://forum.uvvm.org/t/socmake-now-supports-uvvm/474 "2025-02-02T11:33:51Z")
Sorry, I had to split the post and remove the links because of the weird restriction for new users Hello UVVM developers, I am maintaining a build system for hardware projects called SoCMake, it is built on top of CMak… --- ## [GHDL and UVVM which releases](https://forum.uvvm.org/t/ghdl-and-uvvm-which-releases/468)
**Author:** [@adamt99](https://forum.uvvm.org/u/adamt99)\ **Replies:** 4\ **Last updated:** [January 25, 2025, 8:51am UTC](https://forum.uvvm.org/t/ghdl-and-uvvm-which-releases/468 "2025-01-25T08:51:19Z")
Hi I am creating some test benches for a client they want to use UVVM with GHDL. I grabbed the latest releases of both. But have some issues compiling the UART example design. How often is GHDL and UVVM tested are ther… --- ## [To\_string() is not working](https://forum.uvvm.org/t/to-string-is-not-working/472)
**Author:** [@Rupesh](https://forum.uvvm.org/u/Rupesh)\ **Replies:** 2\ **Last updated:** [January 23, 2025, 10:53am UTC](https://forum.uvvm.org/t/to-string-is-not-working/472 "2025-01-23T10:53:08Z")
When we try to compile a file which consists the to\_string function compiler is throwing error CONSTANT UVVM: natural :=24; CONSTANT STR:string:=to\_string(UVVM); This is the logic that has thrown errors (attached to t… --- ## [VVC with Sequencer](https://forum.uvvm.org/t/vvc-with-sequencer/461)
**Author:** [@bryan](https://forum.uvvm.org/u/bryan)\ **Replies:** 1\ **Last updated:** [January 20, 2025, 5:14pm UTC](https://forum.uvvm.org/t/vvc-with-sequencer/461 "2025-01-20T17:14:24Z")
I would like some advice on including my Sequencer (GEN) in the VVC. I created a multiple verification components for 30 busses using UVVM light a few years ago. I appreciate how easy it was to get started and how quic… [Next page](https://forum.uvvm.org/latest.md?page=1)