# VVC Framework **URL:** https://forum.uvvm.org/c/vvc-framework/9.md [Latest](https://forum.uvvm.org/latest.md) · [Categories](https://forum.uvvm.org/categories.md) · [Tags](https://forum.uvvm.org/tags.md) --- ## [About the VVC Framework category](https://forum.uvvm.org/t/about-the-vvc-framework-category/175)
**Author:** [@Marius](https://forum.uvvm.org/u/Marius)\ **Replies:** 0
--- ## [Can I randomize the AXI4 VVC ready signal](https://forum.uvvm.org/t/can-i-randomize-the-axi4-vvc-ready-signal/506)
**Author:** [@beandigital](https://forum.uvvm.org/u/beandigital)\ **Replies:** 1\ **Last updated:** [November 20, 2025, 6:52am UTC](https://forum.uvvm.org/t/can-i-randomize-the-axi4-vvc-ready-signal/506 "2025-11-20T06:52:34Z")
Is it possible to randomize the full AXI4 bus ready signals? --- ## [Increase to Queue Size not acted on](https://forum.uvvm.org/t/increase-to-queue-size-not-acted-on/488)
**Author:** [@Pete](https://forum.uvvm.org/u/Pete)\ **Replies:** 4\ **Last updated:** [September 9, 2025, 2:34pm UTC](https://forum.uvvm.org/t/increase-to-queue-size-not-acted-on/488 "2025-09-09T14:34:41Z")
Hi, I’m getting the following error: UVVM: UVVM: \*\*\* TB\_WARNING #1 \*\*\* UVVM: 12875098160 ns UART\_VVC,1,RX UVVM: Queue is now at 950 of 1000 elements. UVVM: UVVM: UVVM: ==================… --- ## [Transaction info with questasim 2022.4](https://forum.uvvm.org/t/transaction-info-with-questasim-2022-4/500)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 3\ **Last updated:** [June 11, 2025, 7:01pm UTC](https://forum.uvvm.org/t/transaction-info-with-questasim-2022-4/500 "2025-06-11T19:01:52Z")
Hi I try to develop a DUT model and some custom VVCs, I start to develop all things with modelsim 10.6d, next I move to questasim 2022.4. When I run test under modelsim, model works well but all go wrong in questasim. I… --- ## [Exit the await\_completion method](https://forum.uvvm.org/t/exit-the-await-completion-method/496)
**Author:** [@EZA](https://forum.uvvm.org/u/EZA)\ **Replies:** 1\ **Last updated:** [May 6, 2025, 11:59am UTC](https://forum.uvvm.org/t/exit-the-await-completion-method/496 "2025-05-06T11:59:09Z")
Hi all, I want to know if there is a way to exit the await\_completion method. This is the scenario: I have a DUT with a GPIO and a VVC that checks this GPIO. In my TB I have a process for generate stimulus for the DUT… --- ## [VVC Pipelined and out of order transactions](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489)
**Author:** [@AlexK](https://forum.uvvm.org/u/AlexK)\ **Replies:** 1\ **Last updated:** [April 15, 2025, 5:17pm UTC](https://forum.uvvm.org/t/vvc-pipelined-and-out-of-order-transactions/489 "2025-04-15T17:17:00Z")
Hallo, how do I tell to my testbench to pipeline the transcations with a single command ? Currently I use the await\_completion(…) command after every axi\_write or axi\_read. Is there a way to tell the VVC to always carry… --- ## [Adding a Generator to VVC](https://forum.uvvm.org/t/adding-a-generator-to-vvc/460)
**Author:** [@bryan](https://forum.uvvm.org/u/bryan)\ **Replies:** 1\ **Last updated:** [December 23, 2024, 4:03pm UTC](https://forum.uvvm.org/t/adding-a-generator-to-vvc/460 "2024-12-23T16:03:56Z")
I worked on building a library or UVVM components for 30+ bus protocols for a company a few years ago using the UVVM light. The effort went well and the different Bus Functional Models, Checkers, Monitors were relativel… --- ## [Wait until scoreboard is empty](https://forum.uvvm.org/t/wait-until-scoreboard-is-empty/465)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 1\ **Last updated:** [December 23, 2024, 3:42pm UTC](https://forum.uvvm.org/t/wait-until-scoreboard-is-empty/465 "2024-12-23T15:42:28Z")
Hi guys! It’s possible for a VVC wait until the scoreboard is not empty and if SB is not filled in a certain amount of time raise an alert? I must check if a signal in a interface “A” is high but it must be high if val… --- ## [Possible error in documentation?](https://forum.uvvm.org/t/possible-error-in-documentation/450)
**Author:** [@Gastone](https://forum.uvvm.org/u/Gastone)\ **Replies:** 1\ **Last updated:** [June 14, 2024, 6:13am UTC](https://forum.uvvm.org/t/possible-error-in-documentation/450 "2024-06-14T06:13:06Z")
Hi! I try to use scoreboard in conjunction with my own VVC. I follow the example in “UVVM\_VVC\_Framework\_essential mechanism.pdf”. I understand the examples at pg 11 and 12 13… but IMHO they are wrong. If I use this pie… --- ## [Verification components for GRLIB](https://forum.uvvm.org/t/verification-components-for-grlib/424)
**Author:** [@Alo](https://forum.uvvm.org/u/Alo)\ **Replies:** 0\ **Last updated:** [March 5, 2024, 3:48pm UTC](https://forum.uvvm.org/t/verification-components-for-grlib/424 "2024-03-05T15:48:20Z")
Hi, im going to use some GRLIB IPs on a project…is there any UVVM verification component available for GRLIB? Did anybody already use GRLIB IPs and how did he test test them? Thanks! --- ## [Compilation error in the VVC commond methods after setting t\_vvc\_result as record](https://forum.uvvm.org/t/compilation-error-in-the-vvc-commond-methods-after-setting-t-vvc-result-as-record/420)
**Author:** [@Med87](https://forum.uvvm.org/u/Med87)\ **Replies:** 1\ **Last updated:** [February 20, 2024, 1:56pm UTC](https://forum.uvvm.org/t/compilation-error-in-the-vvc-commond-methods-after-setting-t-vvc-result-as-record/420 "2024-02-20T13:56:55Z")
Hi, after defining the t\_vvc\_result as a record in the vvc\_cmd\_pkg, i got the following compilation error: Compiling into bitvis\_vip\_avalon\_mm: uvvm/uvvm\_vvc\_framework/src\_target\_dependent/td\_vvc\_framework\_common\_meth… --- ## [UVVM compilation warning using VUNIT](https://forum.uvvm.org/t/uvvm-compilation-warning-using-vunit/418)
**Author:** [@Med87](https://forum.uvvm.org/u/Med87)\ **Replies:** 2\ **Last updated:** [February 15, 2024, 1:55pm UTC](https://forum.uvvm.org/t/uvvm-compilation-warning-using-vunit/418 "2024-02-15T13:55:27Z")
I’m using the VUNIT to execute unit tests and introduced lately the UVVM framework to my testbench to get advantage of its structure and available VCs as the avalon MM. I noticed that the scoreboard feature wasnt workin… --- ## [How to get two VVC's on a procedure](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238)
**Author:** [@Eric](https://forum.uvvm.org/u/Eric)\ **Replies:** 2\ **Last updated:** [November 26, 2021, 5:53am UTC](https://forum.uvvm.org/t/how-to-get-two-vvcs-on-a-procedure/238 "2021-11-26T05:53:07Z")
Hi, I want to move UVVM code to a package. I want to create procedures where two (or more) different VVC’s I have this working for one VVC \ ... library bitvis\_vip\_spi; use bitvis\_vip\_spi.… --- ## [Copy n Paste error in VVC Framework Manual](https://forum.uvvm.org/t/copy-n-paste-error-in-vvc-framework-manual/244)
**Author:** [@khennigs](https://forum.uvvm.org/u/khennigs)\ **Replies:** 1\ **Last updated:** [November 25, 2021, 6:25am UTC](https://forum.uvvm.org/t/copy-n-paste-error-in-vvc-framework-manual/244 "2021-11-25T06:25:06Z")
Hello @all! i am new to uvvvm and at the moment i am reading a lot of your documentation to get more knowledge and spi vvc up and running. Hoping this is the right place and its ok for you to get simple feedback like … --- ## [UVVM VVC Creation from BFMs](https://forum.uvvm.org/t/uvvm-vvc-creation-from-bfms/237)
**Author:** [@bdecelles](https://forum.uvvm.org/u/bdecelles)\ **Replies:** 2\ **Last updated:** [November 3, 2021, 3:32pm UTC](https://forum.uvvm.org/t/uvvm-vvc-creation-from-bfms/237 "2021-11-03T15:32:35Z")
First off Thank for creating the UVVM Lib. It was selected and used on the current project for creatin 20+ BFMs for multiple busses based on UVVM Util. On the next project we may use the VVC Framework. I am looking f… --- ## [Multiple VVCs question (1 testbench, 1 test harness, 1 test sequencer process?)](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212)
**Author:** [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Replies:** 32\ **Last updated:** [June 23, 2021, 5:14pm UTC](https://forum.uvvm.org/t/multiple-vvcs-question-1-testbench-1-test-harness-1-test-sequencer-process/212 "2021-06-23T17:14:51Z")
Hi Marius, The FPGA has different modules which require to be verified in Simulation. Currently using UVVM & building the BFMs / VVCs to verify different individual FPGA modules. Using at the moment 1 testbench (TB ins… --- ## [UVVM VVC of a simple counter (having issues getting it to simulate with counter\_vvc in place)](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209)
**Author:** [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Replies:** 20\ **Last updated:** [June 7, 2021, 8:11am UTC](https://forum.uvvm.org/t/uvvm-vvc-of-a-simple-counter-having-issues-getting-it-to-simulate-with-counter-vvc-in-place/209 "2021-06-07T08:11:16Z")
Hi, I am new to the UVVM VVC creation. I am trying to convert my current verification platform to using VVC. I generated the templates by executing the python vvc\_generator.py for my counter DUT. Looked at the followi… --- ## [Can we ignore the following vcom-1236, vcom-1346 & vcom-1090 simulation compilation warnings?](https://forum.uvvm.org/t/can-we-ignore-the-following-vcom-1236-vcom-1346-vcom-1090-simulation-compilation-warnings/211)
**Author:** [@KevNug](https://forum.uvvm.org/u/KevNug)\ **Replies:** 4\ **Last updated:** [June 1, 2021, 2:59pm UTC](https://forum.uvvm.org/t/can-we-ignore-the-following-vcom-1236-vcom-1346-vcom-1090-simulation-compilation-warnings/211 "2021-06-01T14:59:08Z")
Hi, I implemented the UVVM VVC framework for our simple counter DUT & created my own testbench. Simulation runs ok but Modelsim reported the following warnings which are all related to the template scripts. Wondering… --- ## [Getting semaphore error when using parallel processes](https://forum.uvvm.org/t/getting-semaphore-error-when-using-parallel-processes/158)
**Author:** [@Hannu](https://forum.uvvm.org/u/Hannu)\ **Replies:** 10\ **Last updated:** [May 26, 2021, 1:24pm UTC](https://forum.uvvm.org/t/getting-semaphore-error-when-using-parallel-processes/158 "2021-05-26T13:24:05Z")
Hi We are running tests in multiple processes. DUT initialization is done in one process and then the tests are run in parallel processes. Register writes/reads are done through VVC methods in the parallel processes. Pr… --- ## [How to read data back in the sequencer from VVC component](https://forum.uvvm.org/t/how-to-read-data-back-in-the-sequencer-from-vvc-component/99)
**Author:** [@Riyazria](https://forum.uvvm.org/u/Riyazria)\ **Replies:** 11\ **Last updated:** [September 29, 2020, 6:14am UTC](https://forum.uvvm.org/t/how-to-read-data-back-in-the-sequencer-from-vvc-component/99 "2020-09-29T06:14:01Z")
Hi, I was trying to implement a simple UVVM environment for my DUT where I am able to drive the data from the sequencer to the VVC component successfully, But when i am trying to read the data back from the VVC compone… --- ## [Documentation needs update](https://forum.uvvm.org/t/documentation-needs-update/94)
**Author:** [@Eric](https://forum.uvvm.org/u/Eric)\ **Replies:** 2\ **Last updated:** [September 14, 2020, 7:33am UTC](https://forum.uvvm.org/t/documentation-needs-update/94 "2020-09-14T07:33:46Z")
Hi, I’m using UVVM 20200623 release. In the folder ..\\uvvm\_vvc\_framework\\doc is the file VVC\_Framework\_Documentation\_Overview.txt. It states: \[…\] UVVM general introduction and user information At this stage given v… --- ## [FIFO, queue, stack "thread-safety"](https://forum.uvvm.org/t/fifo-queue-stack-thread-safety/53)
**Author:** [@lenazh](https://forum.uvvm.org/u/lenazh)\ **Replies:** 1\ **Last updated:** [May 5, 2020, 5:14pm UTC](https://forum.uvvm.org/t/fifo-queue-stack-thread-safety/53 "2020-05-05T17:14:30Z")
Hi All, I’ve been looking at the general data structures (fifo, queue, stack) provided in uvvm\_vvc\_framework/src. I’ve been wondering if they would work for inter-process communication in a testbench. Do I need to enfo…